Signal Integrity in AMS IC
This course studies essential blocks for wire-line communication integrated circuits such as analog equalizer circuits, Decision-Feedback Equalization (DFE), Phase Looked Loop (PLL) and Clock and Data Recovery (CDR) circuits. True understanding of system level modeling and behavioral of the PLL will be discussed. Matlab/Simulink Modeling techniques will be introduced as new vehicle for system level design and simulation. Performance metrics, such as random jitter, BER, jitter transfer, jitter tolerance, phase noise, will be introduced. Integrated circuit design consideration for the key essential blocks for PLL and equalizer block will be covered. Prerequisite: EE 221.
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