Description
Basic constructs of Verilog/VHDL; modeling techniques; chip-level and system level design. Compilation, simulation, source-level debugging, and synthesis. Design exercises and major project carried out in open lab.
Prerequisite: EE 118.
Misc/Lab: Lecture 2 hours/lab 3 hours.
Repeatable
Repeatable for credit
Grading
Normal Grade Rules
Units
3
Page last generated: 08/01/2008 12:11:49
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