Description
Review of system timing for pipelined structures. ARM processor and its Advanced Microprocessor Bus Architecture (AMBA) protocol. The fundamentals of SRAM, SDRAM and E2PROM and their interfaces with AMBA. Direct Memory Access (DMA) design and its interface with AMBA. Verilog skills are required for the labs.
Prerequisite: CMPE 125 and CMPE 127 (with grades of "C" or better in each).
Misc/Lab: 2 hours seminar/3 hours lab.
Grading
Normal Grade Rules
Units
3
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