Description
Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches.
Prerequisite: CMPE 125 (with grade of "C" or better); ENGR 100W.
Misc/Lab: Lecture 2 hours/lab 3 hours.
Grading
Normal Grade Rules
Units
3
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