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CMPE 140

Computer Architecture and Design

Description
Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. Prerequisite: CMPE 125 (with grade of "C-" or better), Computer Engineering or Software Engineering Majors Only. Misc/Lab: Lecture 2 hours/lab 3 hours.

Grading
Normal Grade Rules

Units
3