Description
Digital system building blocks, data path and control units, system-level RTL design, Verilog HDL for design and verification, contemporary design flow and methodology, lab experiments using industry standard CAD tools and field programmable gate array (FPGA) devices.
Prerequisite: CMPE 124 (with grade of "C" or better).
Misc/Lab: Lecture 2 hours/lab 3 hours.
Grading
Normal Grade Rules
Units
3
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