Description
Passive RCL circuit analysis leading to transmission lines in chip wiring and I/O. NMOS and PMOS transistor I-V characteristics and large-signal equivalent circuits. Inverter ratio, bell curve, noise margin and power. Transistor-sizing in simple and complex CMOS gates to achieve optimum performance, area and power. Rise/Fall times, Rise/Fall delays in CMOS gates. Pass-gate circuits, flip-flops, latches and SRAM. BiCMOS circuits.
Prerequisite: EE 101 (with grade of "CR"), MATH 123 or MATH 133A ( with a grade of "C" or better).
Corequisite: CMPE 124.
Misc Lab: Lecture 2 hours/lab 3 hours.
Grading
Normal Grade Rules
Units
3
Page last generated: 08/01/2008 12:11:47
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